Along with the functional progress and miniaturization of electronic devices in recent years, electronic parts have become highly integrated and are mounted at a high density. Semiconductor packages used in these electronic devices have become more and more miniaturized.
Packages using a lead frame of the type which has been generally used have a limitation to downsizing. For this reason, an area mounting-type package method in which chips are mounted on a circuit board (e.g., ball grid array (BGA) and chip scale package (CSP)) has been proposed. In such semiconductor packages, as a method for connecting a semiconductor chip to be mounted on a BGA package with a board, a wire bonding method, a tape automated bonding (TAB) method, a flip-chip (FC) method, and the like are known. In these days, many types of BGA and CSP structures using a flip-chip bonding method advantageous for miniaturization of a semiconductor package are proposed.
A semiconductor package having semiconductor chips mounted on a board has generally been used. As a board used for such semiconductor packages, a substrate having a core layer and a buildup layer has been used (for example, Patent Document 1).
Generally, the coefficient of linear expansion of the substrate (board) differs from that of the semiconductor chip. A substrate is formed from a material containing an organic resin and has a larger coefficient of linear expansion than that of a semiconductor chip. For this reason, if a semiconductor package of a structure having a semiconductor chip mounted on a substrate receives a heat history, the substrate warps due to the difference in coefficient of linear expansion between the substrate and the semiconductor chip. In common semiconductor packages, such warpage may cause cracks and peeling in semiconductor chips, at the interface between a semiconductor chip and a bump, at the interface between a bump and a substrate, and the like.
In addition to this problem, a substrate having a buildup layer which is abundantly used in recent years has a problem. As such a substrate, those having a buildup layer on a core layer have been used in general. Since the clock frequency of semiconductor chips is rapidly increasing, a substrate capable of reducing inductance is desired for mounting semiconductor chips. In a substrate having a core layer and a buildup layer, the inductance of the core layer through-holes is very large. In order to respond to the requirement for reducing the inductance, use of a substrate having a core layer as thin as possible has been proposed.
Generally, the core layer is provided in order to reduce the coefficient of linear expansion of the substrate. Therefore, when the core layer thickness is reduced, the coefficient of linear expansion of the substrate increases because the coefficient of linear expansion of a buildup layer is large. That is to say, there is a stronger tendency for producing cracks and peeling in semiconductor chips, at the interface of a semiconductor chip and a bump, at the interface of a bump and a substrate, and the like.
(Patent Document 1) Japanese Patent Application Laid-open No. 2005-191243
However, the combination of materials that have been used heretofore could not necessarily prevent cracks and peeling without fail.